Flex Differential ADC - 14 Bit 2MSPS

The Flex Differential ADC design includes a robust front end (FE) input buffer, paired with carefully engineered anti-aliasing RC filters to preserve signal integrity. The input supports a 0 to VREF (2.5V, 3.3V, or 4.096V) voltage range on both of its differential inputs. Thanks to the on board negative bias generator circuit, the front end op amps inputs and outputs can truly swing down to 0V ground, unlocking accurate low-level measurements with no bias voltages needed. A rock-solid precision low drift voltage reference for the ADC guarantees stability and precision. The design features power input noise filtering to ensure low noise analog measurements from the ADC.

Benefits of a pseudo-differential ADC input:
--> Stronger noise immunity, especially common mode noise. Great for sensors with long cable runs that can pick up noise
--> Reduced ground noise or loop errors
--> Improved dynamic range for small signals, essentially acts like a 15 bit ADC
--> Flexible since it can easily be converted into single-ended ADC input by grounding or biasing one of the inputs

Pseudo-differential ADC limitations: The input signals cannot be negative in regards to ground and the common mode voltage is fixed at half of the reference voltage or VREF / 2.

The Flex Differential ADC has a specified sample rate up to 2MSPS using a 40MHz SPI clock signal. Can be over clocked up to 4MSPS using 80MHz SPI clock signal but measured signal amplitude will be reduced approximately by half

--> Pseudo differential ADC input supports 14 bits of resolution and a max sample rate of 2MSPS. Can be over clocked to 4MSPS with reduced amplitude

--> Input voltage range of each differential channel (+IN and -IN) is 0 to VREF (2.5V,3.3V, or 4.096V). The ADC returns a code that is equal to +IN - -IN. Each differential input gets a full 14 bit scale or codes from 0 to 16383, which is equivalent to 15 bits of resolution across both inputs

--> Measurement accuracy (uncalibrated) is about +/- 1.2mV (4.8 LSB) at full scale or about ±0.058% of reading. --> Performing a simple two point calibration on the ADC can yield accuracies ~±0.25 mV (1 LSB) around room temp.

--> Design can be powered by a 5V power source. Max current consumption is ~ 10mA (includes digital power)

--> An optional digital supply input for the SPI communication can be added if the digital logic voltage is different than the analog voltage supply, range: 1.8V to 5V. Digital power max current ~3mA.

--> Front end input circuit includes 1Mohm input termination, 750kHz anti-alias filter, buffer amp to drive ADC input, and charge bucket filter to prevent measurement glitches

--> Includes second "raw" ADC input configured as single ended input with no front end or input filter

5% discount for quantities of 10 or above, automatically applied at checkout. Contact Anabit for bulk pricing on quantities of 50 or more.