How Chop Mode Improves Analog to Digital Converter (ADC) Accuracy
Chop Mode, sometimes called ADC Chopping, is a feature found in precision Sigma Delta (ΣΔ) Analog to Digital Converters (ADCs) that helps improve measurement accuracy. In particular Chop Mode reduces offset error internal to the ADC by multiple orders of magnitude. It also reduces random noise in ADC measurements. But the benefits of Chop Mode do come with the tradeoff of increased measurement latency. In this tutorial we will take a look at the technical details of how Chop Mode works, its benefits on measurement accuracy, and its effects on measurement speed.
What is Chop Mode and How it Cancels Out Offset Error
Chop mode is a feature almost exclusively found in high resolution differential Sigma Delta ADC architectures. It is typically found in lower sample rate ADCs since it does reduce the overall measurement speed of the ADC as we shall see in the next section. Figure 1 shows a block diagram of a Sigma Delta ADC with built-in chop mode capabilities. Chop mode works by averaging two consecutive ADC conversions together, but with the important note that the polarity of the second measurement is the reverse of the first measurement. This polarity reversal hardware can be seen in figure 1 with the double pole double throw (DPDT) switch setup. The last step before averaging the two readings together is multiplying the reading made with the polarities reversed by -1.
Figure 1. Block diagram of a Sigma Delta ADC with built-in Chop Mode
Let's look at the math to see how the offset voltage is cancelled out. From figure 1, the offset voltage error is represented as Vos and its polarity can be either positive or negative, as long as it is a constant value.
First ADC reading: (Vin+ - Vin-) + Vos
Second ADC reading (polarities reversed): -1 x (Vin- - Vin+) + Vos
Averaging the readings: [((Vin+ - Vin-) + Vos) - ((Vin- - Vin+) + Vos)] / 2
Averaging result: [(2 x Vin+) - (2 x Vin-)] / 2 = Vin+ - Vin-
As you can see in the result the offset voltage or Vos was canceled out during the averaging process and we are left with the standard differential voltage measurement. It is important to note that chop mode only corrects for offset error within the chop mode loop, which is internal to the ADC. Offset error that is external to the ADC IC will not be corrected or canceled by chop mode.
Understanding the Added Measurement Latency of Chop Mode
When doing single shot ADC measurements the latency of using chop mode is going to be at least the time it takes to make two measurements. But on top of that there is typically an extra delay time added in between the two measurements to allow for settling after the polarity reversal switching.
Single measurement timing: (2 x Measurement Conversion Time) + Settling delay
If you are making continuous ADC measurements the 2x measurement conversion time often occurs only for the first measurement. After the first measurement most ADCs that employ chop mode will buffer the previous measurement and toggle the polarity of the DPDT switch from one measurement to the next:
First measurement: (Measurement1 + Measurement2) + Settling delay
Second Measurement (Measurement2 buffered): Measurement3 + Settling delay
Continuous Measurements (Measurement(n-1) buffered): Measurement(n) + Settling delay
The settling time delay when the polarity reversal switching occurs is dependent on the ADC. If you are using hardware pins to time when a measurement is ready, this delay will automatically be included with the total overall conversion time. If you are using software based timing you will need to ensure you account for the settling time delay in your software measurement timing, see ADC datasheet.
Chop Mode Offset Error Cancelling In Action
Figure 2 shows a the voltage offset error specification from Texas Instrument's ADS1263 ADC. As you can see from Figure 2, the datasheet provides an offset voltage and offset voltage drift specification for when chop mode is off (red lines) and when it is on (green lines). With chop mode on the typical voltage offset goes from 350 uV to < 1uV.
Figure 2. ADS1263 Voltage Offset Specification
The following is demonstration from Anabit's Precision Logger reference design, which uses the ADS1263 ADC, showing the benefit of chop mode. Figure 3, shows a screen shot of a high accuracy voltmeter that is measuring a voltage source output of 1VDC. This measurement serves as our reference and is considered the "true" value of the voltage source for our chop mode demonstration.
Figure 3. Reference voltage measurement using high accuracy voltmeter
Next we measured the same DC voltage level with the Precision Logger with chop mode off. Our software setup printed each measured reading out to a serial terminal (see figure 4). As you can see the measured values from the precision logger are off from our reference measurement by a little over 250uV.
Figure 4. Precision Logger measurements with chop mode off
The measurements in figure 4 are close to the true value in figure 3, but chop mode allows us to do even better. Figure 5 is the same measurement setup but this time with chop mode enabled on the ADC. As you can see, chop mode gives us about a 200uV accuracy improvement and puts us within 50uV of the true value shown in figure 3. This accuracy improvement aligns pretty well with the offset specification shown in figure 2 considering semiconductor companies are pretty conservative with their specifications.
Figure 5. Precision Logger measurements with chop mode on
To learn more about Anabit's Precision Logger click here.
How Chop Mode Reduces Measurement Noise
A nice secondary benefit of using chop mode is it reduces noise since you are averaging two readings together. For the noise reduction to work, the noise must be random noise. Averaging two readings together leads to a noise reduction multiplier of 1/√2 or 0.707. This leads to a Signal to Noise Ratio (SNR) improvement of 3dB. Any consecutive averaging of ADC readings can also be considered Oversampling, by averaging 2 readings together you can get a resolution gain of 0.5 bits. To learn more about oversampling click here to check out our tutorial.
ADC Chop Mode Tutorial Summary and Additional Resource
In this tutorial we looked at a feature found in some high resolution differential Sigma Delta ADCs called chop mode or ADC chopping. Chop mode helps improve ADC measurement accuracy by greatly reducing voltage offset error internal to the ADC. As a secondary benefit, chop mode also reduces random noise by 0.707 in your measurement since you are averaging two measurements together. The only drawback to chop mode is increased measurement time. When making continuous ADC measurements this increased measurement time is reduced by buffering the previous measurement. But there is extra latency always present based on settling time for polarity reversal switching.